MICS=00, MOE=0, DUF=0
SAI MCLK Control Register
| RESERVED | no description available |
| MICS | MCLK Input Clock Select 0 (00): MCLK divider input clock 0 selected. 1 (01): MCLK divider input clock 1 selected. 2 (10): MCLK divider input clock 2 selected. 3 (11): MCLK divider input clock 3 selected. |
| RESERVED | no description available |
| MOE | MCLK Output Enable 0 (0): MCLK signal pin is configured as an input that bypasses the MCLK divider. 1 (1): MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled. |
| DUF | Divider Update Flag 0 (0): MCLK divider ratio is not being updated currently. 1 (1): MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set. |